

The example below demonstrates how signals behave differently than variables. They can cause a lot of confusion and often are hard to synthesize by the tools. In general, I would recommend that beginners avoid using variables. In sequential code, signals are used to create flip-flops, which inherently do not immediately take the value of their assignment. In combinational code, signals immediately take the value of their assignment. The most important thing to understand (and the largest source of confusion) is that variables immediately take the value of their assignment, whereas signals depend on if the signal is used in combinational or sequential code.

Word clock signal code#
Signals depend on if it’s combinational or sequential code to know when the signal takes the value of the assignment.

The most obvious difference is that variables use the := assignment symbol whereas signals use the <= assignment symbol. It is an active high signal that indicates that the output buffer is empty and thus data received from the processor can be loaded to it for conversion. Various audio over Ethernet systems use communication protocols to distribute word clock. S/PDIF, AES/EBU, MADI, ADAT, and TDIF are some of the formats that use a word clock. Word clock is so named because it clocks each audio sample. They can both be used to hold any type of data assigned to them. In digital audio electronics, a word clock or wordclock is a clock signal used to synchronise other devices, such as digital audio tape machines and compact disc players, which interconnect via digital audio signals. Variables and Signals in VHDL appears to be very similar.
